High speed I/O pad and pad/cell interconnection for flip chips

Gridded I/O pads for flip-chip packages in which a coaxial-like solder bump pad configuration is used in which the I/O pads closest to the signal or bump pad are power or ground pads. The ground pads surrounding the signal pad form a coaxial-like pad configuration for impedance matching at the trans...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Tao, Yuming, Little, Vernon R
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:Gridded I/O pads for flip-chip packages in which a coaxial-like solder bump pad configuration is used in which the I/O pads closest to the signal or bump pad are power or ground pads. The ground pads surrounding the signal pad form a coaxial-like pad configuration for impedance matching at the transition from die to package substrate. The ground pads surrounding the signal pad may be connected by a metal trace to form a ground pad ring. The invention employs conductor-backed ground coplanar waveguides (GCPW), which match impedance at connections between I/O cells and signal pads to enhance signal transmission, avoid reflection and leakage, and provide superior electromagnetic shielding. The present invention also supports high quantities of I/Os for a given die size, and supports flexible power and ground placement.