Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etching

Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etching

A method of fabricating an electronic chip on a wafer in which a first mask at a predetermined lower resolution is developed on the wafer and then etched under a first set of conditions for a predetermined period to achieve a mask that is below the resolution limit of current lithography. The etched...

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Bibliographische Detailangaben
Hauptverfasser: Brown, Jeffrey J, Deshpande, Sadanand Vinayak, Horak, David V, Surendra, Maheswaran, Tsou, Len Y, Yang, Qingyun, Yu, Chienfan, Zhang, Ying
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:A method of fabricating an electronic chip on a wafer in which a first mask at a predetermined lower resolution is developed on the wafer and then etched under a first set of conditions for a predetermined period to achieve a mask that is below the resolution limit of current lithography. The etched mask is then used as a hard mask for etching material on a lower layer.