CMOS performance enhancement using localized voids and extended defects

CMOS performance enhancement using localized voids and extended defects

The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and a longitudinal compressive stress on the PFETs, by implanting in the sources and drains if the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drai...

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Hauptverfasser: Dokumaci, Omer H, Chidambarrao, Dureseti, Hegde, Suryanarayan G
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Sprache:eng
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creator Dokumaci, Omer H
Chidambarrao, Dureseti
Hegde, Suryanarayan G
description The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and a longitudinal compressive stress on the PFETs, by implanting in the sources and drains if the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drains of the PFETs ions from the fourth and sixth columns of the periodic table.
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fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_06858488</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>06858488</sourcerecordid><originalsourceid>FETCH-uspatents_grants_068584883</originalsourceid><addsrcrecordid>eNrjZHB39vUPVihILUrLL8pNzEtOVUjNywDRual5JQqlxZl56Qo5-cmJOZlVqSkKZfmZKcUKiXkpCqkVJal5KUChlNS01OSSYh4G1rTEnOJUXijNzaDg5hri7KFbWlyQCFRaUhyfXpQIogzMLEwtTCwsjIlQAgAhgDTo</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>CMOS performance enhancement using localized voids and extended defects</title><source>USPTO Issued Patents</source><creator>Dokumaci, Omer H ; Chidambarrao, Dureseti ; Hegde, Suryanarayan G</creator><creatorcontrib>Dokumaci, Omer H ; Chidambarrao, Dureseti ; Hegde, Suryanarayan G ; International Business Machines Corporation</creatorcontrib><description>The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and a longitudinal compressive stress on the PFETs, by implanting in the sources and drains if the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drains of the PFETs ions from the fourth and sixth columns of the periodic table.</description><language>eng</language><creationdate>2005</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6858488$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64015</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6858488$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Dokumaci, Omer H</creatorcontrib><creatorcontrib>Chidambarrao, Dureseti</creatorcontrib><creatorcontrib>Hegde, Suryanarayan G</creatorcontrib><creatorcontrib>International Business Machines Corporation</creatorcontrib><title>CMOS performance enhancement using localized voids and extended defects</title><description>The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and a longitudinal compressive stress on the PFETs, by implanting in the sources and drains if the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drains of the PFETs ions from the fourth and sixth columns of the periodic table.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2005</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZHB39vUPVihILUrLL8pNzEtOVUjNywDRual5JQqlxZl56Qo5-cmJOZlVqSkKZfmZKcUKiXkpCqkVJal5KUChlNS01OSSYh4G1rTEnOJUXijNzaDg5hri7KFbWlyQCFRaUhyfXpQIogzMLEwtTCwsjIlQAgAhgDTo</recordid><startdate>20050222</startdate><enddate>20050222</enddate><creator>Dokumaci, Omer H</creator><creator>Chidambarrao, Dureseti</creator><creator>Hegde, Suryanarayan G</creator><scope>EFH</scope></search><sort><creationdate>20050222</creationdate><title>CMOS performance enhancement using localized voids and extended defects</title><author>Dokumaci, Omer H ; Chidambarrao, Dureseti ; Hegde, Suryanarayan G</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_068584883</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2005</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Dokumaci, Omer H</creatorcontrib><creatorcontrib>Chidambarrao, Dureseti</creatorcontrib><creatorcontrib>Hegde, Suryanarayan G</creatorcontrib><creatorcontrib>International Business Machines Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Dokumaci, Omer H</au><au>Chidambarrao, Dureseti</au><au>Hegde, Suryanarayan G</au><aucorp>International Business Machines Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CMOS performance enhancement using localized voids and extended defects</title><date>2005-02-22</date><risdate>2005</risdate><abstract>The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and a longitudinal compressive stress on the PFETs, by implanting in the sources and drains if the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drains of the PFETs ions from the fourth and sixth columns of the periodic table.</abstract><oa>free_for_read</oa></addata></record>
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title CMOS performance enhancement using localized voids and extended defects
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-26T07%3A16%3A43IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Dokumaci,%20Omer%20H&rft.aucorp=International%20Business%20Machines%20Corporation&rft.date=2005-02-22&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E06858488%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true