CMOS performance enhancement using localized voids and extended defects

CMOS performance enhancement using localized voids and extended defects

The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and a longitudinal compressive stress on the PFETs, by implanting in the sources and drains if the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drai...

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Hauptverfasser: Dokumaci, Omer H, Chidambarrao, Dureseti, Hegde, Suryanarayan G
Format: Patent
Sprache:eng
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Zusammenfassung:The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and a longitudinal compressive stress on the PFETs, by implanting in the sources and drains if the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drains of the PFETs ions from the fourth and sixth columns of the periodic table.