Method and system for testing the logic of a complex digital circuit containing embedded memory arrays

A method and system for testing the logic of a complex digital circuit containing embedded memory arrays. One embodiment provides for a process which first creates a model for the memory array in the circuit. Next, the memory array is loaded with values representing the model. For example, the memory array may be modeled as a wire by loading each memory location with its address. In this fashion, the data output of the memory array will be equal to the input address. Next a test pattern is generated, based upon the model of the memory array. The memory array is prevented from being written while the test pattern is scanned into the circuit. In this fashion, the output of the memory array is predictable and the output of the circuit may be monitored to determine if the combinational logic has any defects.