Method of fabricating a heterojunction bipolar transistor

A method of fabricating a III-V heterostructure semiconductor device. The method includes the steps of forming at least one conductive post overlying a semiconductor region to form a structure, encapsulating the structure and the conductive post to form a planarized cured passivation layer, and expo...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Hamm, Robert Alan, Kopf, Rose Fasano, Ryan, Robert William, Tate, Alaric, Wang, Yu-Chi
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!