High speed physical circuits of memory interface

A memory interface for a switching router in a network communications system. The interface operates at 200 MHz PLL clock using high speed transistor logic I/O buffers. The interface allows transfer of clock synchronization signals along with the data signals. This allows the setup/hold times to be optimized for an inbound or outbound data pipeline. During writes, data is at least driven one clock cycle after the address. The interface provides flexibility by utilizing at least two clock cycles in order to accommodate a myriad of memory devices (e.g., burst mode SSRAMs having HSTL I/O). In operation, most of the data transfers through the interface are either direct reads or lookup reads. The interface stores writes are stored in a buffer in order to reduce bus turn around penalties.