Master slice type semiconductor integrated circuit and method for designing the same

A placing and wiring method for a master slice type semiconductor integrated circuit is provided. The method is conducted by an automatic placing and routing apparatus with respect to a master slice having a plurality of basic cells formed in a matrix, in which first and second power source wirings and that traverse the plurality of basic cells are connected to a plurality of signal wirings that are formed along a vertical direction to provide connections within each of the plurality of basic cells and/or between the plurality of basic cells . The method includes: a first step of registering in the automatic pacing and routing apparatus definitions of effective pin positions A-A, B-Band C-C; a second step of registering a net list in the automatic placing and routing apparatus; and a third step of determining the placement of pin positions and wiring routes, based on data for the definitions of the effective pin positions and the net list. The registered effective pin positions are provided on lattice grids located inside and outside a region between the first and second power source wirings and . In the circuit wired according to the definitions, contacts with respect to the drains are provided inside and outside the region between the first and second power source wirings and , and the signal wirings do not cross the power source wirings.