VIA0 etch process for FRAM integration

A ferroelectric memory device comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereof for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and reference voltage on the second bit line.