Methods and apparatus for improved efficiency in pipeline simulation and emulation

The present invention relates generally to improvements in the simulation and emulation of multi-stage pipelined processors. In particular, the present invention describes advantageous methods and apparatus for eliminating a large quantity of redundant information during the simulation process. This reduction results in reduced numbers of saving and copying steps in the process of simulating or emulating the behavior of multi-parallel-stage VLIW array processors, such as the Manifold array (ManArray) processor. Techniques for achieving the effects of significantly reducing the amount of computer memory needed to simulate the behavior of a multi-stage pipelined processor, as well as, significantly increasing the performance of the simulation process by eliminating the storing and copying of redundant information are described. These beneficial effects are achieved by reordering the chronological sequence of execution of software models of the various pipeline stages with respect to the actual instruction-flow sequence implemented by the processor hardware. This approach takes advantage of the independence of the stages within a cycle to make the results computed by a previous stage directly available to its subsequent stage without the use of transient data space or data copying. In particular, it is shown how to apply this technique to the simulation of a multi-parallel-stage VLIW array processor, such as the manifold array (ManArray) processor.