Scan interface chip (SIC) system and method for scan testing electronic systems

The present invention relates to the field of electrical integrated circuit testing. More particularly, the present invention relates to a scan test interface utilized to facilitate a system level scan test architecture. A can test interface system and method provides an interface between upstream scan test devices and downstream scan test devices. In one embodiment, the present invention utilizes a scan test interface comprising a scan interface chip (SIC) that facilitates a flexibly programmable system level scan test architecture. The SIC includes a scan test interface register, a system interface, a scan test interface controller, a board interface and a selection circuit.