Process-robust alignment mark structure for semiconductor wafers

The present disclosure relates generally to semiconductor device manufacturing and, more particularly, to a process-robust alignment mark structure for semiconductor wafers. An alignment mark structure for use upon a semiconductor substrate is disclosed. In an exemplary embodiment, the alignment mark structure includes a plurality of segments arranged in an alignment pattern, with each of the plurality of segments being formed from a base pattern created on the substrate. The base pattern includes a plurality of sizes, wherein each of the plurality of sizes of the base pattern is repeated throughout an entire length of each of the plurality of segments.