Apparatus for reducing soft errors in dynamic circuits

The present invention relates to the field of integrated circuits; more specifically, it relates to reducing soft errors in integrated circuits that include dynamic circuits. BACKGROUND OF THE INVENTION Dynamic circuits, such as domino circuits, for example, are widely used in high-speed integrated circuit designs. This is because dynamic circuits typically provide area and speed advantages over corresponding static complementary metal oxide semiconductor (CMOS) circuits. An integrated circuit that includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected and also includes a circuit for selectable alteration of the soft error susceptibility of the dynamic logic gate.