Unified apparatus and method to assure probe card-to-wafer parallelism in semiconductor automatic wafer test, probe card measurement systems, and probe card manufacturing

The invention is directed towards the field of semiconductor automatic test equipment, and more specifically, towards probe card-to-wafer parallelism (also described as planarity) in semiconductor automatic test equipment at wafer probe. A planarization gauge assures probe card-to-wafer parallelism in semiconductor automatic test equipment (ATE) used for wafer test, and provides a standard system reference plane during the building and testing of ATE components. The planarization gauge has two planar and parallel surfaces that may serve as a system reference plane. The planarization gauge has at least one access hole for a depth gauge, and at least one optical target recognizable by a prober's upward looking camera. The planarization gauge is mechanically interchangeable with a probe card; thus, it is compatible with different planarization methods and platforms used in building and testing ATE components. The planarization gauge is manufactured and inspected in a manner as to assure traceability to established standards such as NIST. When used by all ATE vendors, the planarization gauge ensures correlation between the vendors' various planarization methods.