Single port random access memory equipped with a relief module to operate as a dual port shared memory

This invention relates to central processor units and, in particular, to the use of a single-port Random Access Memory (RAM) that is shared between the Central Processing Unit and a State Machine. The present relief module equipped random access memory avoids the need for enforced idle cycles for the processors, thereby enabling the State Machine to operate at its maximum speed. This relief module equipped random access memory also enables the Central Processing Unit to access the data in the single-port Random Access Memory as required to read and write the data contained therein. This is accomplished by the addition of a single-port Random Access Memory module to the plurality of Random Access Memory modules that are typically specified for a particular application. The extra Random Access Memory module alternates its output with each of the others of the plurality of Random Access Memory modules, on a sequential basis, thereby providing effectively extra clock cycles for each Random Access Memory module.