Semiconductor device array having dense memory cell array and hierarchical bit line scheme

The present invention relates generally to semiconductor memory devices, and more particularly to the memory cell arrays and surrounding circuitry of semiconductor memory devices. A semiconductor device architecture () is disclosed. Like unit circuits (), arranged in rows and columns, are coupled to...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	Ogata, Yoshihiro
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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