Semiconductor device array having dense memory cell array and hierarchical bit line scheme

The present invention relates generally to semiconductor memory devices, and more particularly to the memory cell arrays and surrounding circuitry of semiconductor memory devices. A semiconductor device architecture () is disclosed. Like unit circuits (), arranged in rows and columns, are coupled to lower conductive segments (). The lower conductive segments () are arranged in an "open" configuration, allowing adjacent unit circuits () be accessed simultaneously. The lower conductive segments () are coupled to higher conductive segments () by reconnector circuits (and ). The higher conductive segments () are arranged into folded pairs (and ) between differential-type amplifiers (and ). The reconnector circuits (and ) each have a reconnect configuration and a switch configuration. In a reconnect configuration, the reconnector circuits (and ) couple adjacent folded higher conductive segment pairs to one another. In a switch configuration, the reconnector circuits (and ) couple a matching lower conductive segment () to each higher conductive segment of the adjacent higher conductive segment pairs.