Method of optimizing the design of electronic systems having multiple timing constraints

The present invention relates to computer-assisted methods and apparatus for generating or compiling electronic designs such as designs for digital integrated circuits. More specifically, the invention relates to improvements in using timing information while compiling electronic designs. An electronic representation of the electronic design is received which includes various connections between various blocks specifying functions performed within the electronic design. Each of the connections forms part of one or more paths through at least a portion of the electronic design. Each path has an associated timing constraint. The method assigns criticality values to at least one of the connections. These criticality values are based upon a slack ratio that is a function of the timing constraints and values of slack for paths on which the connections reside. The electronic representation may be revised in a manner that biases the representation toward a state in which connections having relatively high criticality are not changed in a manner which increases the delay in those connections or are changed in a manner that reduces delay. In some cases, the timing constraints for a path, and possibly all coupled paths, are relaxed when a connection has a negative slack ratio, negative slack, or routability problems.