High voltage transistor and method for fabricating the same

This application claims benefit of priority under 35 U.S.C. § 119 to Korean Application Serial No. 2001-23181 filed Apr. 28, 2001, the entire contents of which are incorporated by reference herein. In a high voltage transistor and a method for fabricating the same, a semiconductor substrate includes first, second, and third regions, the second and third regions neighboring the first region with boundaries. The first and second drift regions are respectively formed in the second and third regions at a first depth. Insulating films are formed at a second depth less than the first depth, having a predetermined width respectively based on the boundary between the first and second regions and the boundary between the first and third regions. A channel ion injection region is formed with a variable depth along a surface of the semiconductor substrate belonging to the first region and the insulating films. A gate insulating film is formed on the channel ion injection region, partially overlapping the insulating films at both sides around the channel ion injection region. Drain and source regions are formed within the first and second drift regions, respectively, and a gate electrode is formed to surround the gate insulating film and to partially overlap the insulating films.