Method of packaging a plurality of devices utilizing a plurality of lead frames coupled together by rails

1. Field of the Invention A method and arrangement for packaging a plurality of chip devices. The method includes providing a plurality of bottom leadframes coupled together with rails to form a bottom leadframe assembly and providing a plurality of top leadframes coupled together with rails to form a top leadframe assembly. Dies are placed between the top and bottom leadframes and the top and bottom leadframe assemblies are coupled to one another. The dies are attached to die attach pads of the bottom leadframes and are coupled to the top leadframes with solder bumps. A molded body is placed around the top and bottom leadframes with the dies therebetween and the rails are removed from the top and bottom leadframes, thus providing a plurality of chip devices.