Scan interface chip (SIC) system and method for scan testing electronic systems

The present invention relates to the field of electrical integrated circuit testing. More particularly, the present invention relates to a scan test interface utilized to facilitate a system level scan test architecture. A scan test interface system and method provides an interface between upstream scan test devices and downstream scan test devices. The scan test interface system and method receives scan test signals, facilitates flexible configuration of scan test signals and transmits scan test signals on subordinate scan test chains. A scan test interface includes a scan test interface register, a system interface, a scan test interface controller, a board interface and a selection circuit.