Clock generation circuits and methods with minimal glitch generation and systems using the same

The present invention relates in general to integrated circuits and in particular to clock generation circuits and methods with minimal glitch generation and systems using the same. A clock generator circuit includes a counter which counts edges of a received clock signal and a comparator which comp...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: Duewer, Bruce Eliot
Format: Patent
Sprache:eng
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:The present invention relates in general to integrated circuits and in particular to clock generation circuits and methods with minimal glitch generation and systems using the same. A clock generator circuit includes a counter which counts edges of a received clock signal and a comparator which compares divide ratio control data with a count generated by the counter and generates an active state of a control signal in response. An output flip-flop toggles in response to the control signal and a selected edge of the received dock signal to toggle a state of an output clock signal.