Single poly EEPROM with reduced area

The invention relates to improved EEPROM devices and methods of making same and, more particularly, the invention relates to an EEPROM with reduced area. Still more particularly, the present invention relates to a reduced area EEPROM device with dielectric coupling capacitance between poly lines. An EEPROM () comprises a source region (), a drain region (); and a polysilicon layer (). The polysilicon layer () comprises a floating gate comprising at least one polysilicon finger (A-E) operatively coupling the source region () and drain region () and a control gate comprising at least one of the polysilicon fingers (A-E) capacitively coupled to the floating gate. The EEPROM () has a substantially reduce area compared to prior art EEPROM since an n-well region is eliminated.