Apparatus and method for conditionally flushing a pipeline upon a failure of a test condition

The invention relates to computers and microprocessor architectures. Particularly, this invention relates to emulation of an instruction set architecture (ISA) using another instruction set architecture. More particularly, this invention relates to a method of and apparatus for emulating branch instructions of an instruction set architecture using instructions from another instruction set architecture. A method and apparatus that utilizes a simple test and flush mechanism to implement branch instructions of one Instruction Set Architecture (ISA) using instructions of another ISA is described. During the decoding and sequencing of microinstructions to implement a branch instruction, a fix-up address, which represents the remedial branch target in the event of a mispredicted target or branch condition, is determined and stored. A test condition is set to determine if the prediction or the branch condition was correct. When the test condition fails, the instruction execution pipeline is immediately flushed to avoid executing any instruction remaining in the pipeline following the branch instructions. The flushing of the pipeline signals the instruction fetch control mechanism to redirect the instruction flow to the instruction corresponding to the fix-up address. A method and apparatus according to the present invention further allows flushing of the pipeline when conditions other than ones involved in branch instructions occurs, e.g., to flush stale instructions.