Programmable throttle circuit for each control device of a processing system

In a processing system, a number of devices including a central processing unit (CPU) and memory are coupled to a time shared processor bus through which digital words are transferred from one device to another under software task control of the CPU or other control device. These control devices generally operate autonomously to perform certain tasks according to some sequence. For example, in which is a time graph exemplifying a control device, like a CPU or DMA controller, for example, carrying out tasks , , and in a predetermined sequence. In performing these tasks, the control device generally requires access to the processor bus and more than one control device may require access to the processor bus concurrently in order to carry out their individual tasks. A bus arbiter is generally provided to regulate access to the bus among the various control devices requiring access according to a predetermined priority scheme to prevent collisions. However, when permitted, access is limited to the performance of only one or two cycles of the task, but not the entire task in order to prevent any one control device from dominating access to the bus. A processing system comprises: a shared system resource; a plurality of control devices, each assignable with a task having a predetermined maximum time to complete, the control devices time sharing the system resource in the process of performing their assigned tasks in accordance with a predetermined sequence; and an arbiter circuit for regulating access of said control devices to the system resource. Each control device includes a throttle circuit coupled to the arbiter circuit and individually programmable to control in cooperation with the arbiter circuit utilization of the system resource by the corresponding control device so that each control device may perform its task within the predetermined maximum completion time thereof.