XOR circuit

The present invention relates to an electronic bus and more particularly to a high-speed, digital serial bus interface. An XOR circuit includes XOR function logic. One advantage of the XOR circuit is that the complements of A and B are not required. The XOR circuit receives an enable signal that disables all the load transistors to eliminate static power dissipation of the XOR circuit and always force the output high when disabled. The output signal of the XOR function logic does not swing rail-to-rail and also has a relatively low drive level. To overcome that, cascade transistor stages are used that have small increments in device sizes, preferably widths, between stages. This allows the fastest rise/fall times at the output of the XOR function logic.