Method for calculation of cell delay time

The present invention relates to a delay calculation method and to a layout optimization method for high-accuracy delay time calculation of cells and wires in timing verification during the design of a semiconductor integrated circuit. Today, because of advances in semiconductor process technology, the size of transistors have been miniaturized and reduced down to less than 0.5 m (submicron size). Also with respect to rooting of wires, both the wire pitch and the wire width tend toward being shrunk. Therefore, when calculating a length of time taken for a signal to propagate in a large-scale integrated circuit (hereinafter called the "delay time"), it now becomes necessary to pay attention to the influence of the resistance of a wire and the influence of an adjacent wire. These influences have not been taken into much consideration so far. In a circuit simulation step, a cell transistor level net list is input, the slew of an input signal waveform and the magnitude of a load capacitance connected to a cell output terminal are varied for each cell, to perform a circuit simulation of each cell for obtaining an output signal waveform. Next, in a dependence table generation step, the dependence of the output signal waveform slew upon the input slew rate and the load capacitance is calculated for each cell, the dependence thus calculated is compared with a predetermined threshold level, and according to the dependence level, a delay calculation expression with consideration taken to the delay of signal propagation between the cell input and output terminals and another without such consideration are selectively used. Accordingly, the delay times of the cells forming a semiconductor integrated circuit can be calculated at high accuracy and at high processing speed.