Methods of forming patterns and molds for semiconductor constructions

The invention pertains to methods of forming patterns for semiconductor constructions, and in particular applications pertains methods of utilizing contact lithography for forming patterns. The invention also encompasses molds configured to pattern masses associated with semiconductor constructions. The invention includes methods of forming patterns in low-k dielectric materials by contact lithography. In a particular application, a mold having a first pattern is pressed into a low-k dielectric material to form a second pattern within the material. The second pattern is substantially complementary to the first pattern. The mold is then removed from the low-k dielectric material. The invention also includes a method of forming a mold; and includes a mold configured to pattern a mass over a semiconductor substrate during contact lithography of the mass.