Self-aligned process for fabricating memory cells with two isolated floating gates

The present invention relates to a self-aligned, scalable non-volatile memory (NVM) cell having two isolated floating gates in a single transistor. The present invention also relates to a method for fabricating such an NVM cell. A self-aligned process for fabricating a non-volatile memory cell having two isolated floating gates. The process includes forming a gate dielectric layer over a semiconductor substrate. A floating gate layer is then formed over the gate dielectric layer. A disposable layer is formed over the floating gate layer, and patterned to form a disposable mask having a minimum line width. Sidewall spacers are formed adjacent to the disposable mask, and source/drain regions are implanted in the substrate, using the disposable mask and the sidewall spacers as an implant mask. The disposable mask is then removed, and the floating gate layer is etched through the sidewall spacers, thereby forming a pair of floating gate regions. The sidewall spacers are removed, and an oxidation step is performed, thereby forming an oxide region that surrounds the floating gate regions. A control gate is then formed over the oxide region.