Fabrication method of semiconductor integrated circuit device and its testing apparatus

The present invention relates to a technique for fabricating a semiconductor integrated circuit device and a testing apparatus therefor; and, more specifically, the invention relates to a technique that can be applied, for example, to a burn-in test and probe test of a semiconductor integrated circu...

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Bibliographische Detailangaben
Hauptverfasser: Ban, Naoto, Namba, Masaaki, Hasebe, Akio, Wada, Yuji, Kohno, Ryuji, Seito, Akira, Motoyama, Yasuhiro
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:The present invention relates to a technique for fabricating a semiconductor integrated circuit device and a testing apparatus therefor; and, more specifically, the invention relates to a technique that can be applied, for example, to a burn-in test and probe test of a semiconductor integrated circuit device, and effectively can be applied particularly to a burn-in test of a semiconductor device in the wafer condition, that is, to a so-called wafer level burn-in test. A testing apparatus and a fabricating method of a semiconductor integrated circuit device for reducing the fabrication cost by placing, in the wafer level burn-in, divided contactors in equally contact with the full surface of wafer, enabling repair of each contactor and improving the yield of contactors. The cassette structure of the mechanical pressurizing system in the testing apparatus is structured with a plurality of divided silicon contactor blocks and a guide frame for integrating these blocks and employs the wafer full surface simultaneous contact system of the divided contactor integration type. Each probe of the silicon contactor is equally placed in contact in the predetermined pressure with each test pad of each chip of the test wafer by mechanically pressuring each silicon contactor block which moves individually, the test control signal is supplied to each chip and this test result signal is obtained for the wafer level burn-in test.