Design circuit pattern for test of semiconductor circuit

1. Field of the Invention At a level in which high density and miniaturization of wiring of integrated circuits is required to such an extent that optical proximity effect and the correction of optical proximity effect is necessary, a test design pattern having many test patterns corresponding to design conditions is produced, wherein each test pattern can be evaluated at a practical level. A design circuit pattern for test of a semiconductor circuit comprises a circuit pattern having a plurality of circuits formed on a semiconductor wafer wherein each of the circuits is designed for test according to an individual design condition as the object of electrical measurement. The design circuit pattern for test of a semiconductor circuit comprises a group of test cells each formed of a circuit of the object of electrical measurement and evaluation formed according to individual conditions and having a switch or switches connected with on one end or both ends thereof. A decoder generates on/off signals for a switch or switches provided within the group of test cells for specifying an evaluated test cell chosen from the group of test cells for electrical measurement and evaluation. One or more address pads provide electrical signals for specifying the evaluated test cell to the decoder. An input pad provides an electrical input signal of the evaluated test cell and an output pad outputs an electrical output signal of the evaluated test cell. One or more contrastive evaluated test cells are provided apart from the group of test cells. A contrastive evaluated input pad for inputting electrical signals is directly connected with one end of the contrastive evaluated test cells and is provided for every contrastive evaluated test cell. A contrastive evaluated output pattern for obtaining electrical signals is directly connected with the other end of the contrastive evaluated test cells and is provided for every contrastive evaluated test cell.