Memory hole modification and mixed technique arrangements for maximizing cacheable memory space

The present invention is directed to efficient defining of cacheable memory space. More particularly, the present invention is directed to memory hole modification and mixed technique arrangements for maximizing cacheable memory space. Cache defining arrangements for maximizing cacheable memory space, including a mixed technique scheme using a bottom-up scheme defining a first non-memory-hole portion using mainly substantially additive blocks of cacheable space, and a top-down scheme defining a second non-memory-hole portion by defining an oversized block of cacheable space and using mainly substantially subtractive blocks of cacheable space.