Silicon oxide based gate dielectric layer

In a field effect transistor ("FET"), a capacitance is associated with a gate dielectric layer, which insulates a gate electrode from a channel disposed within a semiconductor substrate. As semiconductor devices continue to be scaled down to reduce power consumption, the demand for higher input FET capacitances has increased. The input capacitance of a FET may be increased by either reducing the thickness of the gate dielectric layer or increasing its dielectric constant. A semiconductor device having a dielectric layer formed between a first and a second conductive layer. The dielectric layer comprising a layer of silicon oxide, SiO, having a dielectric constant greater than about 3.9 and less than or equal to about 12.