Scan chain connectivity

The present invention relates in general to an integrated circuit (IC) and, in particular, to using scan chains for applying inputs or receiving outputs from the IC where the scan chains have a functional as well as a test operation. Scan chains are designed for an IC based on test coverage for functional logic units, Before physical placement the scan circuit elements are assigned scan attributes which define which scan circuit elements must remain coupled and also defines which groups of scan circuit elements must remain in selected groups. The scan chains and the logic are physically placed and location data on the scan circuit elements are determined from the placement data. Using the scan attributes, single scan circuit elements and scan circuit elements that must remain connected (sub-scan chains) are re-allocated across a same number of new scan chains. These scan circuit elements are rewired using an algorithm that minimizes scan path lengths within the new scan chains.