Method for implementing shared channel decoder for onboard processing satellites

The present invention relates to method for implementing a single chip shared channel decoder supporting a multiplicity of variable bit rate carriers. More particularly, the present invention relates to a method for decoding an input signal comprising a plurality of channel symbols utilizing Viterbi decoding for use in onboard processing satellites in which trade-offs are made between memory for storing the survivor paths and bit error rate performance. A decoding method and apparatus, using the Viterbi algorithm for selecting survivor paths terminating on each trellis state, applied for realization of a shared channel decoder (SCD). The shared channel decoder include a branch metric calculator for calculating branch metrics B, a plurality of ACS units for computing and exchanging new path metrics and survivor paths E, a memory (RAM) for storing new path metrics and survivor paths E, and a memory (RAM) for storing previous path metrics and previous survivor paths E. The branch metrics Bis the set of branch metrics for decoding step t (e.g., for a code rate of ½, B={B, B, B, B}), the path metrics is the set of S survivor metrics { , , . . . , } at decoding step t and the survivor paths Eis the set of S survivor metrics {E,E, . . . , E} where S is the number of decoder states. In one embodiment, the shared channel decoder includes a branch metric queue for storing branch metrics B, a tentative path metric memory for storing tentative path metrics , and a multiplexer (selector) for selecting the previous path metrics when t≠T+cD, and selecting the tentative path metrics when t=T+cD. In an alternative embodiment, the size of required RAM is traded off against the decoder BER performance, but tentative path metrics are not stored when t=(c+1)D. Instead, when t=T+cD, the state j having best path metric is selected and the contents of the survivor register, denoted by E, are output as the D decoded bits.