Architecture, method(s) and circuitry for low power memories

Architecture, method(s) and circuitry for low power memories

The present invention relates to memory circuits generally and, more particularly, to an architecture, method and/or circuit for implementing a low power memory. A method for providing at least 2 Meg of SRAM cells having a maximum average operating current of approximately 9.43 mA comprising the ste...

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Hauptverfasser: Ford, Keith A, Gradinariu, Iulian C, Georgescu, Bogdan I, Mulholland, Sean B, Silver, John J, Rose, Danny L
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Sprache:eng
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creator Ford, Keith A
Gradinariu, Iulian C
Georgescu, Bogdan I
Mulholland, Sean B
Silver, John J
Rose, Danny L
description The present invention relates to memory circuits generally and, more particularly, to an architecture, method and/or circuit for implementing a low power memory. A method for providing at least 2 Meg of SRAM cells having a maximum average operating current of approximately 9.43 mA comprising the steps of (A) providing an address path configured to consume a maximum average operating current of approximately 2.38 mA, (B) providing one or more sense amplifiers configured to consume a maximum average operating current of approximately 0.91 mA, (C) providing one or more bitlines configured to consume a maximum average operating current of approximately 0.94 mA and (D) providing a Q path configured to consume a maximum average operating current of approximately 0.61 mA.
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A method for providing at least 2 Meg of SRAM cells having a maximum average operating current of approximately 9.43 mA comprising the steps of (A) providing an address path configured to consume a maximum average operating current of approximately 2.38 mA, (B) providing one or more sense amplifiers configured to consume a maximum average operating current of approximately 0.91 mA, (C) providing one or more bitlines configured to consume a maximum average operating current of approximately 0.94 mA and (D) providing a Q path configured to consume a maximum average operating current of approximately 0.61 mA.</description><language>eng</language><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6674682$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64039</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6674682$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Ford, Keith A</creatorcontrib><creatorcontrib>Gradinariu, Iulian C</creatorcontrib><creatorcontrib>Georgescu, Bogdan I</creatorcontrib><creatorcontrib>Mulholland, Sean B</creatorcontrib><creatorcontrib>Silver, John J</creatorcontrib><creatorcontrib>Rose, Danny L</creatorcontrib><creatorcontrib>Cypress Semiconductor Corp</creatorcontrib><title>Architecture, method(s) and circuitry for low power memories</title><description>The present invention relates to memory circuits generally and, more particularly, to an architecture, method and/or circuit for implementing a low power memory. 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title Architecture, method(s) and circuitry for low power memories
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