Architecture, method(s) and circuitry for low power memories

The present invention relates to memory circuits generally and, more particularly, to an architecture, method and/or circuit for implementing a low power memory. A method for providing at least 2 Meg of SRAM cells having a maximum average operating current of approximately 9.43 mA comprising the steps of (A) providing an address path configured to consume a maximum average operating current of approximately 2.38 mA, (B) providing one or more sense amplifiers configured to consume a maximum average operating current of approximately 0.91 mA, (C) providing one or more bitlines configured to consume a maximum average operating current of approximately 0.94 mA and (D) providing a Q path configured to consume a maximum average operating current of approximately 0.61 mA.