Dynamic logic circuit with beta controllable noise margin

The present invention relates in general to logic circuitry, and in particular, to improving noise margin within a dynamic circuit. A domino logic circuit has a beta controllable noise margin and an ability to hold an evaluated state until a received clock signal goes to a low state by adding an additional N-channel field effect transistor (NFET) in series with another N-channel field effect transistor, where both of these devices receive the date input signal. Additionally, a P-channel field effect transistor (PFET) also receives the data input signal into its gate electrode. This P-channel field effect transistor is positioned so that it opposes one of the N-channel field effect transistors. The advantages gained by this additional circuitry may also be implemented within a multiplexer circuit.