Method and apparatus for reducing average power in RAMs by dynamically changing the bias on PFETs contained in memory cells

This invention relates generally to electronic circuits. More particularly, this invention relates to reducing average power in SRAMs and DRAMs. A circuit for reducing power in SRAMS and DRAMS is implemented by dynamically controlling a voltage applied to Nwells containing PFETs used in memory cells. When a memory cell is in standby, the voltage applied to Nwells containing PFETs is increased in order to reduce leakage current. When a memory cell is being written, read, or refreshed, the voltage applied to Nwells containing PFETs is reduced in order to allow the memory cell to switch more quickly.