Apparatus and system for blocking memory access during DMA transfer

The present invention generally relates to memory access in a computer system. More specifically, the invention relates to memory access during a DMA (Direct Memory Access) transfer. The present invention is directed to an apparatus and system for selectively inhibiting access to a memory during a DMA block transfer. In accordance with one embodiment of the present invention, the system includes memory, a DMA engine, and logic configured so that when a control signal is asserted, the logic blocks the DMA engine's request for access to memory and generates an acknowledgment of the request, such that the DMA engine performs a DMA transfer without accessing data in memory.