Double gate DRAM memory cell having reduced leakage current

The present invention relates generally to semiconductor devices, and more particularly to dynamic random access memory (DRAM) storage cells and arrays. A dynamic random access memory (DRAM) cell and associated array are disclosed. The DRAM cell () includes a storage capacitor () and a pass transistor (). The pass transistor () includes a source region (), drain region () and channel region (). A top gate () is disposed over the channel region () and a bottom gate () is disposed below the channel region (). The top gate () and bottom gate () are commonly driven to provide greater control of the pass transistor () operation, including an off state with reduced source-to-drain leakage. The DRAM array () includes memory cells () having pass transistors () with double-gate structures. Memory cells () within the same row are commonly coupled to a top word line and bottom word line. The resistance of the top and bottom word lines is reduced by a word line strap layer (). The DRAM array () further includes a strapping area that is void of memory cells. Conductive contact between the top word line bottom word line, and word line strap layer () of each row is made within the strapping area by way of strapping vias () and top-to-bottom word line vias ().