In-system programmable flash memory device with trigger circuit for generating limited duration program instruction

The present invention relates to In-System Programmable (ISP) Flash memory devices. In particular, it relates to ISP Flash memory devices that incorporate JTAG test circuitry. A trigger circuit for an In-System Programmable (ISP) memory device that operates with a JTAG interface. The trigger circuit receives instruction signals from the JTAG control circuitry, and limits the duration of these instruction signals to avoid erroneously repeating ISP programming operations. The trigger circuit includes a first logic circuit, a delay circuit, and a second logic circuit. The first logic circuit generates a logic high output when both the JTAG RUN-TEST and a program instruction signal are simultaneously asserted, and causes the second logic circuit to toggle the limited duration instruction signal into a logic high state. The delay circuit also detects the simultaneous assertion of the JTAG RUN-TEST and a program instruction signal, and generates a cancellation signal after a predetermined number of clock cycles. The cancellation signal causes the second logic circuit to toggle the limited duration instruction signal into a logic low state.