Semiconductor storage unit

1. Field of the Invention A semiconductor storage unit is provided with a memory cell array that is sectioned into a plurality of blocks, a redundant memory cell, and a redundant memory cell selection circuit for replacing a defective cell in the memory cell array with the redundant memory cell. The redundant memory cell selection circuit is provided with n-channel MOS transistors (N-N) to whose gates a block selection signal (BLK) is input, p-channel MOS transistors (P-P) to whose gates a block selection signal (BLKB) that is reverse in logical value to the block selection signal (BLK) is input, and fuses (F-F) that are connected between the sources or drains of the transistors (N-N) and those of the transistors (P-P), respectively. Thereby, it is possible to reduce the number of fuses and the size of a chip.