Method and apparatus for providing highly programmable memory mapping and improved interleaving

1. Field of the Invention A method and apparatus for providing highly programmable memory mapping and improved interleaving includes a system address chip that maps a received memory transaction address to an intermediate address for accessing a memory array having at least one individually addressable memory row. During the translation the memory array is logically partitioned into a plurality of individually addressable memory blocks such that each of said memory blocks are interleavingly accessible independent of how said memory array is populated. The apparatus includes logic to generate at least a portion of the intermediate address by combining selected bits of the transaction address with selected bits of a programmed block address based in part upon the received transaction address.