Blocked net buffer insertion
This invention relates to the field of integrated circuit design. More particularly, this invention relates to a method and system for timing optimization during integrated circuit design. A method of determining a desired connection path between a pair of points of a net separated by one or more bl...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | This invention relates to the field of integrated circuit design. More particularly, this invention relates to a method and system for timing optimization during integrated circuit design.
A method of determining a desired connection path between a pair of points of a net separated by one or more blockages, while reducing path delays and ramp time violations and without placing buffers within any of the blockages. |
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