Processing unit in which access to system memory is controlled

The present invention relates to a processing unit equipped with a function of controlling an access (load/store) to a system memory. Particularly, the invention relates to a processing unit capable of improving its processing capacity by reducing the number of synchronization control required at the time of changing over interruption levels (running level). Has an instruction issuing unit that monitors a change in a memory access sequencing model as well as monitoring a change in an interruption level. When the memory access sequencing model has been changed following a change in the interruption level, the instruction issuing unit restricts the issuing of memory access instructions corresponding to the interruption level after the change until when the execution of all the instructions issued before the change in the interruption level has been finished.