Test limits based on position

This invention relates to the field of testing integrated circuits. More particularly the invention relates to a system for determining different failure limits for various electronic characteristics of integrated circuits based on selected subsets of the integrated circuits. A method for testing integrated circuits having associated position designations, where a predetermined set of input vectors is introduced as test input into the integrated circuits. The output from the integrated circuits in response to the predetermined set of input vectors is sensed, and the output from the integrated circuits is recorded in a wafer map, referenced by the position designations. The output from at least a subset of the integrated circuits is selected and mathematically manipulated to produce a reference value. The output for each of the integrated circuits in the selected subset is individually compared to the reference value, and graded integrated circuits within the selected subset that have output that differs from the reference value by more than a given amount are identified. A classification is assigned to the graded integrated circuits and recorded in the wafer map, referenced by the position designations for the graded integrated circuits.