Method and an apparatus for synthesizing a programmable logic circuit

The present invention relates to the field of integrated circuit technology. More specifically an embodiment of the present invention relates to a synthesizable programmable logic architecture. A method for describing a user programmable logic function generator in a Hardware Description Language (HDL), e.g., Verilog is disclosed. The logic function generator includes a multiplexer having a plurality of select inputs and a plurality of programmable data inputs. The logic function generator which can be implemented exclusively with gates generates a function of the select inputs. The logic function generator receives user's input through the plurality of data inputs to generate an output of a desired logic function of the select inputs. The logic function generator is entirely made of standard gates, which is amenable to representation by and inclusion in standard design libraries. The invention further provides a user with greater flexibility by allowing a cascading of a number of logic function generators for generating multi-variable functions generated of a greater number of select inputs.