Routable high-density interfaces for integrated circuit devices
Modern interfaces for Integrated Circuit (IC) packages, chips, and other devices have ever-increasing terminal densities. Many modern IC devices have so many terminals so tightly clustered that it becomes difficult to construct mutually-segregated conductors to connect carrier lines to each terminal...
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Zusammenfassung: | Modern interfaces for Integrated Circuit (IC) packages, chips, and other devices have ever-increasing terminal densities. Many modern IC devices have so many terminals so tightly clustered that it becomes difficult to construct mutually-segregated conductors to connect carrier lines to each terminal. Signal-carrying terminals and lines are particularly burdensome, since they must be segregated from each other as well as from power and ground lines. Signal lines on an IC device or carrier must have sufficient electrical isolation from other conductors that undesired coupling and leakage paths are avoided.
Patterns for a routable interface of the signal lines of a integrated circuit device include several groups of terminals distributed about the pattern center, each group clustered along a corresponding curvilinear reference segment extending outward from the pattern center to its perimeter. Routability zones are created between each successive pair of groups. For higher terminal density, in at least one of the terminal groups of the pattern, either the offset of the terminals from the reference line segment is not uniform, or the distance of the terminals from the pattern center does not increase uniformly. A portion, preferably at least about 50% of the terminals in a group of the pattern are not collinear with, but offset from, the reference segment. A portion, preferably at least about 90% of the terminals in a given terminal group are each closer to the reference line segment of that terminal group than they are to the reference segment of another terminal group. The patterns of this invention can be employed on IC chips, IC package layers and PCB layers for patterning of terminals, pins, via, pads and another connector devices useful in IC devices. |
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