Interleaved memory device for burst type access in synchronous read mode with the two semi-arrays independently readable in random access asynchronous mode

The present invention relates in general to memory devices, and, in particular, to an interleaved memory readable in a synchronous mode by successive locations with a sequential type of access commonly referred to as burst mode, and to a standard memory read in a random access asynchronous mode with fast access times. A multipurpose memory device suitable for a broader range of applications, whether requiring the reading of data in an asynchronous mode with random access (as in a standard memory) or in a synchronous sequential mode with sequential or burst type access, is capable of recognizing the mode of access and the mode of reading that is currently required by the microprocessor. The memory device self-conditions its internal circuitry as a function of such a recognition in order to read data in the requested mode without requiring the use of additional external control signals and/or implying a penalization in terms of access time and reading time compared to those which, for the same fabrication technology and state of the art design, may be attained with memory devices specifically designed for either one or the other mode of operation.